Crack FPGA
Keep in Tech! Technical blogs about FPGA Development and Digital Signal Processing Concepts. Also a
Hello Everyone! We are working on rebranding this page so taking a short break. We will be online real soon. Thank you!
22/12/2022
📢 Post Alert!
Are you a hardware developer and looking to get started with VHDL programming language? I'm writing a 10 part blog series about the basics of VHDL, enough to get started and write your own VHDL code for your hardware.
Read the blog here! 👇
https://crackfpga.com/vhdl-basics-part-1/
Follow www.facebook.com/crackfpga for more such blogs!
VHDL BASICS - PART 1 - crackfpga In this series, we discuss the basics of the VHDL programming language, enough to get started and write your own VHDL code for your hardware
22/04/2021
Xilinx FPGA playground is promoting adaptable and intelligent FGPA innovation through education. FPGA Workshop videos are now available for free download.
Click 👇to download!
FPGA Workshop Video Archives Now Available The FPGAuary Giveaway was a huge success! We received over 2,000 signups, over 350 people attended the livestreamed workshop, and prize boxes went out to 20 lucky winners around the world, including in the US, India, Germany, Chile, Hong Kong, and Mexico, to name just a few!
30/03/2021
📢 Post Alert!
Are you looking for a software to program your FPGAs?
Vivado is one such software and its webPACK edition can be downloaded for free.
Read the blog to know-how! 👇
Follow www.facebook.com/crackfpga for more such blogs!
How to download and install Vivado 2020.2 for free - crackfpga In this blog, we will see step by step how to install Vivado 2020.2 for free. Vivado is a software to program your FPGAs.
27/03/2021
See how FPGAs solved the latency challenge due to unprecedented increase in traffic to data centres!
The Future of Adaptive Computing: The Composable Data Center This blog post is excerpted from the keynote presentation of Salil Raje, EVP and GM Xilinx Data Center Group, given March 24, 2021, at Xilinx Adapt: Data Center. To see Salil’s keynote on-demand, along with a great slate of presentations by industry experts, you can register and view the content h...
08/03/2021
Check out this blog from MicroZed Chronicles! 👇
How to configure the processing system (PS) of a custom board?!
MicroZed Chronicles: Configuring a Zynq Processing System on a Custom Board Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author. You may have seen my posts referencing the book I’ve been writing over the last two years with Dan Binnun and Saket Srivastava on how to design embedded systems. When we set out on this jour...
28/02/2021
34 amazing ways engineers are using MATLAB to change the world 🌎
34 Amazing Applications of MATLAB See how engineering and science are changing our world.
25/02/2021
📢 Post Alert!
Are you into Space Technology?
Space exploration is exciting but insanely expensive. Recently, NASA spent $2.7 billion on the Mars Rover Perseverance mission that made a dramatic touchdown last week on the red planet. But remember, space exploration has fueled most of the technological advances and innovations for the same reason. It is apparent from the Mars Rover Perseverance technology that the NASA team has definitely pushed their boundaries to minimize costs and risks.
Follow Crack FPGA for updates!
More on 👇
https://crackfpga.com/nasa-mars-rover-perseverance-technology-highlights/
NASA Mars Rover Perseverance Technology Highlights - crackfpga Are you into Space Exploration and its Technology? Have a look at the Mars Rover Perseverance technology highlights here!
22/02/2021
📢 Post Alert
A simple example to demonstrate how to create AXI-Stream interface for a RTL design in Vivado
👉 Subscribe www.crackfpga.com for more updates!
How to create AXI-Stream Interface for a RTL Design - crackfpga Step by step tutorial to create AXI-Stream interface for RTL designs and how to add it as an IP to the block design in Vivado
18/02/2021
Yes we are!!
Fraunhofer Institutes kicks off 6G research project in Germany Five Fraunhofer Institutes are cooperating to conduct research activities on “6G” technology under the leadership of Fraunhofer IIS. With the project, called 6G Sentinel, the research i…
18/02/2021
A new study confirms Nokia’s leadership in . Read more on our latest blog: https://nokia.ly/3ast3HX
A new study confirms Nokia’s leadership in . Read more on our latest blog: https://nokia.ly/3ast3HX
18/02/2021
A step by step tutorial to create AXI-Stream interface in your Xilinx System Generator design
https://crackfpga.com/create-axi-stream-interface-in-xilinx-system-generator/
How to create AXI-Stream interface in Xilinx System Generator - crackfpga In this tutorial, we will see step by step, how to create AXI-Stream interface in Xilinx System Generator design.
14/02/2021
What does "embedded measurement" mean to you?
https://digilent.medium.com/embedded-measurement-a-digital-transformation-c6241b9a3f18
What does "embedded measurement" mean to you? Steve Johnson, President of Digilent, weighs in on what it means to us.
https://digilent.medium.com/embedded-measurement-a-digital-transformation-c6241b9a3f18
06/02/2021
Do you still have your Game Boy 😉 then maybe you should try this!!
Someone Hacked a Nintendo Game Boy Color to Control Apple TVs The device is a pleasure to look at and even more to use. Come see it for yourself.
06/02/2021
Reducing logic is the most sought solution to the resource utilization problem. So here is a blog post with the solution!
How to optimize MCode by reducing Logic?
https://crackfpga.com/optimize-mcode-by-reducing-logic-part-3/
How to optimize MCode by reducing Logic? - Part 3 - crackfpga A simple BRAM example with resource utilization analysis to show you how reducing logic improves your FPGA resource usage.
04/02/2021
Machine learning code to give you movie recommendations.!
MATLAB, Machine Learning & Movies… The Perfect Combination They say don’t judge a book by its cover, but no one said anything about movies, right?? In today’s post, I am pleased to welcome the winners of the “Most creative use of MATLAB” Award at TAMU Datathon 2020. TAMU Datathon is the world’s first and only Major League Hacking (MLH) Data Scienc...
04/02/2021
Next in the optimization series!! Learn how to reduce LUT usage for your FPGA design.
How to optimize MCode by reducing LUT Usage? - Part 2 - crackfpga Simple design tips and examples to optimize MCode in your system generator design by reducing the LUT usage crackfpga
03/02/2021
NEW YEAR PROMOTION LINK BELOW!!
Are you a beginner to Xilinx vivado ?? Here is a beginner course offered by Udemy for a reduced price for the new year. Check it out!!
VIVADO Xilinx FPGA -Learn From The Beginning (+PCIe project) Learn how to use Vivado design suite to design Xilinx FPGA FROM ZERO using VHDL or VERILOG language!
02/02/2021
New blogpost!!
Part 1 of the series "How to optimize MCode" is out. If you're interested in minimizing resource usage for your FPGA design, this may help!
www.crackfpga.com/optimize-mcode-part1/
How to optimize MCode? - Part 1 - crackfpga Simple design tips and examples to optimize MCode in your system generator design for better resource utilization and performance crackfpga .
Get in Tech!!